Tips for Practical Use: Gate Driving–Part 2

In the previous article, as a matter for study relating to gate driving of full-SiC modules, we explained “False Gate Turn-On”. This time, as part 2 of the same discussion, we explain methods for dealing with false gate turn-on.

Methods for Suppressing False Gate Turn-On

Three methods are described for dealing with false gate turn-on.

In the method of ①, by lowering Vgs to a negative voltage rather than to 0 V, a margin is provided such that even if Vgs rises somewhat, the threshold value is not reached. In this method, a negative gate driving voltage is needed, and so as the gate driver power supplies, asymmetric power supplies such as +18 V/-3 V are used. In this case, the negative voltage must be set so as not to exceed the maximum rating for Vgs.

In ②, an external capacitor is added between the gate and the source to lower the impedance, suppressing rises in the gate potential. As one matter for study, C_GS is also a loss factor, and so the capacitance must be set appropriately.

In ③, a mirror clamp MOSFET is added between gate and source. When the SiC MOSFET is turned off, this MOSFET is turned on to force Vgs to essentially 0 V, eliminating rises in the gate potential.

Confirmation Using an Evaluation Circuit

The effect in suppressing rises in the gate voltage is confirmed using an evaluation circuit. The following is an example of a gate driving circuit; the gate driving L is negative-voltage driving. The +18 V at CN1 and CN4 and the -3 V at CN3 and CN6 are the driving power supplies. C_GS and a mirror clamp MOSFET are added to enable adjustments, including of the gate resistance. This gate driver is connected to the gate and source of the full-SiC power module to check for rises in the gate voltage.

The effect when adding the external capacitor C_GS in ② is first confirmed. To begin with data without the external C_GS is presented. When the low-side gate resistance Rg is reduced, the rise in Vgs increases, as explained in the preceding article.

Next, data is shown for a case in which 2.2 nF is added as the external capacitor C_GS. As indicated by the 2.2 nF curve, rising of the gate voltage is suppressed.

Next, data for a case in which 5.6 nF is added as C_GS is shown. No particular improvement in the suppression effect can be seen even when the capacitance is increased.

As a result, adding C_GS does exhibit an effect in reducing the rise in Vgs, but we see that simply increasing the capacitance does not mean that the effect is increased. As explained above, C_GS is also a cause of losses, and so the value of the capacitor must be set appropriately.

Next, the effect of ③, the mirror clamp MOSFET, is explained. Dots are the data presented above when a capacitor is added, and mirror clamp data is indicated by circles. It is seen that there is a very great effect. The graph on the right indicates that where the surge voltage is concerned, all conditions have about the same effect.

Finally, we present actual waveforms. The green and blue waveforms are from before measures were implemented, and red and orange waveforms are for after implementation. Conditions are as indicated in the table; after measures are implemented, a mirror clamp MOSFET has been added, Rg is reduced from 3.9Ω to 2.2 Ω, and a 5.6 nF capacitor C_GS is added.

After implementing the measures, ringing was reduced in both Id and Vd. Where Vgs is concerned, a rise in Vgs(L) to a peak of 5.9 V was observed, but after the measures were implemented this was held to 1.1 V. In the case of Vgs(H) also, ringing with a peak of 7.7 V was reduced to 3.5 V, and it should be clear that convergence was faster.

In this way, by optimizing gate driving of a full-SiC power module, clean operation with still lower losses is made possible.