Ringing at switching nodes

Before studying the PCB layout of a DC-DC converter, it is necessary to understand that parasitic capacitances and inductances exist in an actual PCB. The effects of these components are unexpectedly large, and it often happens that a circuit, even if designed without problems, may not operate properly depending on the layout, due to insufficient attention being paid to these parasitic components. In this section we shall verify these effects for “Ringing at switching nodes “. When drawing an actual wiring pattern, measures must be taken to deal with parasitic components as necessary.

In this chapter, we shall explain the following topics, but understanding of each will require referencing other topics, and so topic items are listed including planned items.

Actual Circuit Models and Switching Node Ringing

The following diagram indicates parasitic capacitances and inductances in a synchronous rectification step-down DC-DC converter circuit. The blue C and L symbols in the circuit are parasitic. In an actual circuit, there are parasitic capacitances and inductances in the PCB, and when a switch is turned on and off, high-frequency ringing occurs, as indicated in the diagram.

The inductance of printed wiring is of the order 1 nH per millimeter. In other words, if the wiring is unnecessarily long, the wiring inductance increases. Moreover, the rise time (t_r) and fall time (t_f) of a switching MOSFET are generally several nanoseconds. The voltage and current generated due to a parasitic component can be calculated using the following equations.

The length of wiring with an inductance of 10 nH is about 10 mm. It seems like a small length, but if a large current flows, we see that a high voltage is generated.

The ringing frequency band can be calculated as f = 1/time. If t_r and t_f are both 5 ns, then the period can be considered to be 10 ns, and so the frequency band is 100 MHz. In general, switching frequencies tend to range from 500 kHz to 1 MHz, and so ringing occurs at frequencies that are 100 to 200 times higher.

From here, we explain how current is caused to flow by parasitic components in this circuit model. The first diagram is for when a high side MOSFET is turned on. The parasitic capacitance C₂ is charged, energy is stored in the parasitic inductances L₁ to L₅, and when the voltage at the switching node becomes equal to VIN, the energy stored in L₁ to L₅ causes resonance together with C₂, and large ringing occurs.

Next, when the high side MOSFET is turned off, the parasitic capacitor C₂ is again charged, energy is stored in the parasitic inductances L₁ to L₅, and when the voltage at the switching node approaches GND level, the energy stored in L₁ to L₅ cause resonance, this time with C₁, and large ringing results. The energy stored in parasitic inductances and the resonance frequency can be calculated using the equations on the lower right.

The inductance L₄ is determined by the characteristics of C_BYPASS. L₃ and L₅ vary greatly with the PCB layout. This circuit is an example in which a switching transistor is connected externally, but when an IC with an internal switching transistor is used, L₁, L₂ and C₂ are fixed values depending only on the IC, and do not depend on the PCB layout.

In this way, in an actual PCB there are components that do not appear in the circuit diagram, and consequently, for example large ringing may occur at a switching node in conjunction with switching if the PCB layout is not planned carefully, and often this may cause the circuit to not operate properly or to generate considerable noise or the like. The reader can no doubt appreciate the reasoning behind the maxim “keep the wiring short” when it comes to PCB layout. Hereafter, we will explain specific layouts and how to draw wiring.

• DC-DC converter
• MOSFET